1. Field of the Invention
The present invention relates to methods of driving an organic electroluminescence emission portion.
2. Description of the Related Art
In an organic electroluminescence display device (hereinafter simply referred to as “an organic EL display device” for short when applicable) using an organic electroluminescence element (hereinafter simply referred to as “an organic EL element” for short when applicable) as an electroluminescence element, a luminance of the organic EL element is controlled in accordance with a value of a current caused to flow through the organic EL element. Also, a simple matrix system and an active matrix system are well known as a driving method in the organic EL display device as well similarly to the case of a liquid crystal display device. Although the active matrix system has a disadvantage that a structure is more complicated than that based on the simple matrix system, it has various advantages that an image having a light luminance is obtained, and so forth.
A drive circuit composed of five transistors and one capacitor (called a 5Tr/1C drive circuit) is well known as a circuit for driving an organic electroluminescence emission portion (hereinafter simply referred to as “an electroluminescence portion” when applicable) constituting the organic EL element from Japanese Patent Laid-Open No. 2006-215213. As shown in FIG. 19, the 5Tr/1C drive circuit is composed of five transistors of a write transistor TSig, a drive transistor TDrv, an electroluminescence controlling transistor TEL—C, a first node initializing transistor TND1, and a second node initializing transistor TND2, and one capacitor portion C1. Here, a source/drain region on one side of the drive transistor TDrv constitutes a second node TND2, and a gate electrode of the drive transistor TDrv constitutes a first node ND1.
For example, each of the write transistor TSig, the drive transistor TDrv, the electroluminescence controlling transistor TEL—C, the first node initializing transistor TND1, and the second node initializing transistor TND2 is composed of an n-channel thin film transistor (TFT), and the electroluminescence portion ELP is provided on an interlayer insulating film or the like which is formed so as to cover the drive circuit. An anode electrode of the electroluminescence portion ELP is connected to the source/drain region on the one side of the drive transistor TDrv. On the other hand, a voltage VCat (for example, 0 V) is applied to a cathode electrode of the electroluminescence portion ELP. In FIG. 19, reference symbol CEL designates a parasitic capacitance of the drive transistor TDrv.
As shown in a conceptual view of FIG. 20, the organic EL display device includes:
(1) a scanning circuit 101;
(2) a video signal outputting circuit 102;
(3) (M×N) organic EL elements each including the electroluminescence portion ELP, and a drive circuit for driving the electroluminescence portion ELP;
(4) M scanning lines SCL which are each connected to the scanning circuit 101 and which extend in a first direction;
(5) N data lines DTL which are each connected to the video signal outputting circuit 102 and which extend in a second direction different from the first direction (specifically, in a direction intersecting perpendicularly to the first direction);
(6) a power source portion 100;
(7) an electroluminescence controlling transistor controlling circuit 103;
(8) a first node initializing transistor controlling circuit 104; and
(9) a second node initializing transistor controlling circuit 105.
Here, the N organic EL elements 10 are disposed in the first direction, and the M organic EL elements are disposed in the second direction, that is, the (M×N) organic EL elements 10 are disposed in a two-dimensional matrix. It is noted that although the (3×3) organic EL elements 10 are shown in FIG. 20 for the sake of convenience, this is merely an exemplification.
FIG. 21 schematically shows a timing chart in the drive operation in the organic EL elements 10. Also, FIGS. 22A to 22I schematically show an ON/OFF state and the like of the write transistor TSig, the drive transistor TDrv, the electroluminescence controlling transistor TEL—C, the first node initializing transistor TND1, and the second node initializing transistor TND2. As shown in FIG. 21, preprocessing for executing threshold voltage canceling processing is executed for [time period-TP(5)1]. That is to say, each of potentials of a first node initializing transistor controlling line AZND1 and a second node initializing transistor controlling line AZND2 is set at a high level in accordance with the operations of the first node initializing transistor controlling circuit 104 and the second node initializing transistor controlling circuit 105. As a result, as shown in FIG. 22B, the first node initializing transistor TND1 and the second node initializing transistor TND2 are each turned ON, so that a potential at the first node ND1 is set at V0fs (for example, 0 V). On the other hand, a potential at the second node ND2 is set at Vss (for example, −10 V). As a result, a difference in potential between the gate electrode of the drive transistor TDrv, and the source/drain region on the electroluminescence portion ELP side becomes equal to or higher than the threshold voltage Vth (for example, 3 V) of the drive transistor TDrv. Also, the drive transistor TDrv is held in an ON state.
Next, as shown in FIG. 21, the threshold voltage canceling processing is executed for [time period-TP(5)2]. The potential of the second node initializing transistor controlling line AZND2 is set at a low level in and before completion of [time period-TP(5)1], thereby turning OFF the second node initializing transistor TND2 as shown in FIG. 22C. A potential of an electroluminescence controlling transistor controlling line CLEL—C is set at a high level in accordance with the operation of the electroluminescence controlling transistor controlling circuit 103 in a commencement of [time period-TP(5)2] while the ON state of the first node initializing transistor TND1 is maintained. As a result, as shown in FIG. 22D, the electroluminescence controlling transistor TLEL—C is turned ON. As a result, the potential at the second node ND2 changes toward a potential obtained by subtracting the threshold voltage Vth of the drive transistor TDrv from the potential at the first node ND1. That is to say, the potential at the second node ND2 held in a floating state rises. Also, when the difference in potential between the gate electrode and the source/drain region on the electroluminescence portion ELP side of the drive transistor TDrv reaches the threshold voltage Vth of the drive transistor TDrv, the drive transistor TDrv is turned OFF. In this state, the potential at the second node ND2 is held approximately at (V0fs−Vth). After that, for [time period-TP(5)3], while the first node initializing transistor TND1 is held in the ON state, the potential of the electroluminescence controlling transistor controlling line CLEL—C is set at the low level in accordance with the operation of the electroluminescence controlling transistor controlling circuit 103. As a result, as shown in FIG. 22E, the electroluminescence controlling transistor TEL—C is turned OFF. Next, for [time period-TP(5)4], the first node initializing transistor controlling line AZND1 is set at the low level in accordance with the operation of the first node initializing transistor controlling circuit 104, thereby turning OFF the first node initializing transistor TND1 as shown in FIG. 22F.
Next, as shown in FIG. 21, processing for writing data to the drive transistor TDrv is executed for [time period-TP(5)5]. Specifically, as shown in FIG. 22G, while each of the first node initializing transistor TND1, the second node initializing transistor TND2 and the electroluminescence controlling transistor TEL—C is held in the OFF state, a potential of corresponding one of the data lines DTL is set at a voltage [a voltage of a video signal (a drive signal, a luminance signal) VSig used to control the luminance in the electroluminescence portion ELP] corresponding to a video signal. Next, the potential of the corresponding one of the scanning lines SCL is set at the high level, thereby turning ON the write transistor TSig. As a result, the potential at the first node ND1 rises to VSig. The electric charges based on a change in potential at the first node ND1 are distributed to the capacitor portion C1, the parasitic capacitance CEL of the electroluminescence portion ELP, and the parasitic capacitance between the gate electrode and the source/drain region on the electroluminescence portion ELP side of the drive transistor TDrv. Therefore, the potential at the second node ND2 changes so as to follow a change in potential at the first node ND1. However, the change in potential at the second node ND2 becomes small as the capacitance value of the parasitic capacitance CEL of the electroluminescence portion ELP becomes larger. In general, the capacitance value of the parasitic capacitance CEL of the electroluminescence portion ELP is larger than that of each of the capacitor portion C1, and the parasitic capacitance of the drive transistor TDrv. Then, when it is assumed that the potential at the second node ND2 hardly changes, a difference Vgs in potential between the gate electrode, and the source/drain region on the electroluminescence portion ELP side in the drive transistor TDrv is expressed by Expression (1):Vgs≈VSig−(V0fs−Vth)  (1)
After that, as shown in FIG. 21, mobility correcting processing is executed for [time period-TP(5)6]. In the mobility correcting processing, the potential at the source/drain region on the electroluminescence portion ELP side of the drive transistor TDrv (that is, the potential at the second node ND2) is made to rise in accordance with the characteristics (such as the magnitude of a mobility μ) of the drive transistor TDrv. Specifically, as shown in FIG. 22H, while the write transistor TSig is held in the ON state, the electroluminescence controlling transistor TEL—C is turned ON in accordance with the operation of the electroluminescence controlling transistor controlling circuit 103. Next, after a lapse of a predetermined time (t0), the write transistor TSig is turned OFF. As a result, when the value of the mobility μ of the drive transistor TDrv is large, an amount, ΔV (potential correction value), of potential risen at the source/drain region on the electroluminescence portion ELP side in the drive transistor TDrv becomes large. On the other hand, when the value of the mobility μ of the drive transistor TDrv is small, an amount, ΔV (potential correction value), of potential risen at the source/drain region on the electroluminescence portion ELP side in the drive transistor TDrv becomes small. Here, the difference Vgs in potential between the gate electrode, and the source/drain region on the electroluminescence portion ELP side in the drive transistor TDrv is transferred from Expression (1) into Expression (2):Vgs≈VSig−(V0fs−Vth)−ΔV  (2)
It is noted that a predetermined time (a total time t0 of [time period-TP(5)6] demanded to execute the mobility correcting processing has to be previously calculated as a design value when the organic EL display device is designed.
By performing the above operations, the threshold voltage canceling processing, the write processing and the mobility correcting processing are all completed. Also, for subsequent [time period-TP(5)7], the write transistor TSig is held in the OFF state, and the first node ND1, that is, the gate electrode of the drive transistor TDrv is held in the floating state. On the other hand, the electroluminescence controlling transistor TEL—C is held in the ON state, and thus one of the source/drain regions of the electroluminescence controlling transistor TEL—C is held in a state of being connected to a power source portion (a voltage Vcc, for example, 20 V) for controlling the electroluminescence of the electroluminescence portion ELP. Therefore, as the result of the foregoing, as shown in FIG. 21, the potential at the second node ND2 rises, so that the same phenomenon as that in a so-called bootstrap circuit occurs in the gate electrode of the drive transistor TDrv. Thus, the potential as well at the first node ND1 rises. As a result, the difference Vgs in potential between the gate electrode, and the source/drain region on the electroluminescence portion ELP side in the drive transistor TDrv holds the value in Expression (2). In addition, a current caused to flow through the electroluminescence portion ELP is a drain current Ids caused to flow from the drain region into the source region of the drive transistor TDrv. Thus, when it is assumed that the drive transistor TDrv ideally operates in a saturated region, the drain current Ids can be given by Expression (3):
                                                                        I                ds                            =                              k                ·                μ                ·                                                      (                                                                  V                        gs                                            -                                              V                        th                                                              )                                    2                                                                                                        =                              k                ·                μ                ·                                                      (                                                                  V                        gs                                            -                                              V                        th                                            -                                              Δ                        ⁢                                                                                                  ⁢                        V                                                              )                                    2                                                                                        (        3        )            
As shown in FIG. 22I, the drain current Ids is caused to flow through the electroluminescence portion ELP. Also, the electroluminescence portion ELP emits a light with a luminance corresponding to the value of the drain current Ids.